1. Field
The present disclosure relates to electronic-design-automation (EDA) techniques. More specifically, the present disclosure relates to a technique for monitoring the execution of EDA software.
2. Related Art
As semiconductor technology is scaled to ever smaller dimensions, there are commensurate increases in chip complexity. For example, smaller dimensions typically result in chips with an increased number of logic gates and time domains. Moreover, this increase in chip complexity typically results in a significant increase in the time and cost needed to design chips.
In an attempt to address these problems, chip designers are using more sophisticated design techniques. However, the complexity of the resulting EDA software often restricts project visibility, which makes it difficult for chip designers to monitor and manage the large number of design details, including complicated foundry-specific design rules and libraries. As a consequence, chip-design productivity and schedule predictability are often adversely affected. Indeed, the majority of chip-design tape-outs fail to meet their deadlines.
Hence, there is a need for an EDA technique without the above-described problems.